1. Field of the Invention
This invention relates to a liquid crystal display. More particularly, the invention relates to a liquid crystal display device that improves the working efficiency of a liquid crystal display device, as well as reduces manufacturing cost.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to display a picture.
To this end, as shown in FIG. 1, the LCD includes a liquid crystal display panel 2 having liquid crystal cells arranged in a matrix, a gate driver 6 for driving gate lines GL1 to GLn of the liquid crystal display panel 2, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal display panel 2, and a timing controller 8 for controlling the gate driver 6 and the data driver 4.
The liquid crystal display panel 2 includes a thin film transistor TFT provided at each crossing of the gate lines GL1 to GLn and the data lines DL1 to DLm, and a liquid crystal cell 7 connected to the thin film transistor TFT. The thin film transistor TFT is turned on when supplied with a scanning signal, for example, a gate high voltage VGH from the gate line GL, to apply a pixel signal from the data line DL to the liquid crystal cell 7. Further, the thin film transistor TFT is turned off when supplied with a gate low voltage VGL from the gate line GL to keep a pixel signal charged in the liquid crystal cell 7.
The liquid crystal cell 7 can be equivalently represented as a liquid crystal capacitor. The liquid crystal cell 7 includes a pixel electrode connected with a common electrode and a thin film transistor with a liquid crystal therebetween. Further, the liquid crystal cell 7 includes a storage capacitor that maintains a signal level of the charged pixel signal until the next pixel signal is charged. The storage capacitor is provided between the pixel electrode and the pre-stage gate line. Such a liquid crystal cell 7 varies an alignment state of the liquid crystal having a dielectric anisotropy in accordance with a pixel signal charged through the thin film transistor TFT to control a light transmittance, thereby implementing gray scale levels.
The timing controller 8 generates gate control signals (i.e., gate start pulse (GSP), gate shift clock (GSC) and gate output enable (GOE)) and data control signals (i.e., source start pulse (SSP), source shift clock (SSC), source output enable (SOE) and polarity control (POL)) using synchronizing signals V and H supplied from a video card (not shown). The gate control signals (i.e., GSP, GSC and GOE) are applied to the gate driver 6 to control the gate driver 6, while the data control signals (i.e., SSP, SSC, SOE and POL) are applied to the data driver 4 to control the data driver 4. Further, the timing controller 8 aligns red (R), green (G) and blue (B) pixel data VD and applies the data to the data driver 4.
The gate driver 6 sequentially drives the gate lines GL1 to GLn. To this end, the gate driver 6 includes a plurality of gate integrated circuits (IC's) 10 as shown in FIG. 2A. The gate IC's 10 sequentially drive the gate lines GL1 to GLn connected thereto under control of the timing controller 8. Specifically, the gate IC's 10 sequentially apply a gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals (i.e., GSP, GSC and GOE) from the timing controller 8.
The gate driver 6 shifts a gate start pulse GSP in response to a gate shift clock GSC to generate a shift pulse. Then, the gate driver 6 applies a gate high voltage VGH to the corresponding gate line GL every horizontal period in response to the shift pulse. The shift pulse is shifted line-by-line for each horizontal period, and any one of the gate IC's 10 applies the gate high voltage VGH to the corresponding gate line GL to correspond with the shift pulse. The gate IC's supply a gate low voltage, VGL, in a remaining interval when the gate high voltage, VGH, is not supplied to the gate lines GL1 to GLn.
The data driver 4 applies pixel signals for each line to the data lines DL1 to DLm for each horizontal period. The data driver 4 includes a plurality of data IC's 16 as shown in FIG. 2B. The data IC's 16 apply pixel signals to the data lines DL1 to DLm in response to data control signals (i.e., SSP, SSC, SOE and POL) from the timing controller 8. The data IC's 16 convert pixel data VD from the timing controller 8 analog pixel signals using a gamma voltage from a gamma voltage generator (not shown) to output them.
The data IC's 16 shift a source start pulse SSP in response to a source shift clock SSC to generate sampling signals. Then, the data IC's 16 sequentially latch the pixel data VD for a particular unit in response to the sampling signals. Thereafter, the data IC's 16 convert the latched pixel data VD for one line to analog pixel signals, and apply the signals to the data lines DL1 to DLm in an enable interval of a source output enable signal SOE. The data IC's 16 convert the pixel data VD to positive or negative pixel signals in response to a polarity control signal POL.
As shown in FIG. 3, each of the data IC's 16 includes a shift register part 34 for sequential applying sampling signals, a latch part 36 for sequentially latching the pixel data VD in response to the sampling signals to simultaneously output the signals, a digital to analog converter (DAC) 38 for converting the pixel data VD from the latch part 38 to pixel voltage signals, and an output buffer part 46 for buffering pixel voltage signals from the DAC 38 to output them. Further, the data IC 16 includes a signal controller 20 for interfacing various control signals (i.e., SSP, SSC, SOE, REV and POL, etc.) from the timing controller 8 and the pixel data VD, and a gamma voltage part 32 for supplying positive and negative gamma voltages required for the DAC 38.
The signal controller 20 controls various control signals (i.e., SSP, SSC, SOE, REV and POL, etc.) from the timing controller 8 and the pixel data VD in such a manner to be output to the corresponding elements.
The gamma voltage part 32 sub-divides a plurality of gamma reference voltages input from a gamma reference voltage generator (not shown) for each gray level to output them.
Shift registers included in the shift register part 34 sequentially shift a source start pulse SSP from the signal controller 20 in response to a source sampling clock signal SSC to output it as a sampling signal.
The latch part 36 sequentially samples the pixel data VD from the signal controller 20 for a certain unit in response to the sampling signals from the shift register part 34 to latch them. The latch part 36 is comprised of i latches (wherein i is an integer) to latch i pixel data VD, and each of the latches has a dimension corresponding to the bit number of the pixel data VD. Particularly, the timing controller 8 divides the pixel data VD into even pixel data VDeven and odd pixel data VDodd to reduce a transmission frequency, and simultaneously outputs the data through each transmission line. Each of the even pixel data VDeven and the odd pixel data VDodd includes red (R), green (G) and blue (B) pixel data. Thus, the latch part 36 simultaneously latches the even pixel data VDeven and the odd pixel data VDodd supplied via the signal controller 20 for each sampling signal. Then, the latch part 36 simultaneously outputs i latched pixel data VD in response to a source output enable signal SOE from the signal controller 20.
The latch part 36 restores pixel data VD modulated such that the transition bit number is reduced in response to a data inversion selection signal REV to output them. The timing controller 8 modulates the pixel data VD such that the number of transition bits are minimized using a reference value to determine whether the bits should be inverted or not. This minimizes an electro-magnetic interference (EMI) upon data transmission due to a minimal number of bit transactions from LOW to HIGH or HIGH to LOW.
The DAC 38 simultaneously converts the pixel data VD from the latch part 36 to positive and negative pixel voltage signals. The DAC 38 includes a positive (P) decoding part 40 and a negative (N) decoding part 42 commonly connected to the latch part 36, and a multiplexer (MUX) part 44 for selecting output signals of the P decoding part 40 and the N decoding part 42.
The n P decoders included in the P decoding part 40 convert n pixel data simultaneously input from the latch part 36 to positive pixel voltage signals using positive gamma voltages from the gamma voltage part 32. The i N decoders included in the N decoding part 42 convert i pixel data simultaneously input from the latch part 36 to negative pixel voltage signals using negative gamma voltages from the gamma voltage part 32. The i multiplexers included in the multiplexer part 44 selectively output the positive pixel voltage signals from the P decoder 40 or the negative pixel voltage signals from the N decoder 42 in response to a polarity control signal POL from the signal controller 20.
The i output buffers included in the output buffer part 46 are comprised of voltage followers, etc. connected, in series, to the respective i data lines DL1 to DLi. Such output buffers 46 buffer pixel voltage signals from the DAC 38 to apply the signals to the data lines DL1 to DLi.
Such a related art LCD differentiates output channels of the data IC's 16 included in the data driver 4 based upon a resolution of the liquid crystal display panel 2. This is because the data IC's 16 have certain channels connected to the data lines DL for each resolution of the liquid crystal display panel 2. Thus, problems arise in that a different number of data IC's 16 having different output channels for each resolution type of the liquid crystal display panel 2 need to be used. This reduces working efficiency and increases manufacturing cost.
More specifically, for a liquid crystal display having a resolution of an eXtended Graphics Array (XGA) class (i.e., 1024×3) with 3072 data lines DL iF requires four data IC's 16, each of which has 768 data output channels. For a liquid crystal display having a resolution of a Super eXtended Graphics Adapter+ (SXGA+) class (i.e., 1400×3) with 4200 data lines DL it requires six data IC's 16, each of which has 702 data output channels. The remaining 12 data output channels are treated as dummy lines. Additionally, a liquid crystal display having a resolution of a Wide eXtended Graphics Array (WXGA) class (i.e., 1280×3) with 3840 data lines DL, it requires six data IC's 16, each of which has 642 data output channels. In this case, the remaining 12 data output channels are treated as dummy lines. As mentioned above, different data IC's 16 having a specific number of output channels have to be used for each resolution of the liquid crystal display panel 2. As a result, the related art liquid crystal display has a drawback in that the working efficiency is reduced and manufacturing cost is increased.